Bit serial arithmetic in dsp8/30/2023 ![]() ![]() Particularly, in public-key cryptography special features are required for multiplier units. The area limitations for the processors of such systems require small but efficient computational units. Modern VLSI technology allows integrating massive parallel systems on a single chip. In these cases, the bitserial approach became an important alternative for efficient implementation of custom Digital Signal Processing (DSP) circuits. INTRODUCTION In several cases, it is senseless to use a bit-parallel circuit: it has an important cost in area and runs faster than the throughput required by the application. Keywords – systolic arrays, array multipliers, folding technique. In order to illustrate functionality of proposed architecture the preliminary results of FPGA implementation are given. The resulting architecture can operate with operands of arbitrary length. Folding technique is applied to serial-parallel serial multiplier architecture. Tokic 4 1Abstract – The synthesis of new family of folded bit-serial multipliers for integer multiplication is presented in this paper. Family of Folded Bit-Serial Multipliers Vladimir M. ![]()
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